As it is well known, power electronic device packages essentially comprise a power electronic device integrated in a chip or in a die and mounted on a metal frame. The package also comprises some electric connection pins, projecting from a protection body or envelope realized with an insulating plastic material, for example an epoxy resin [Molding compound]. Connection pins allow, once the package is mouned on a printed circuit board, electronic signals to be transmitted between the power electronic devices and the conduction paths defined in the board.
Over the last few years, power device development has been highly sped up in view of reducing more and more the overall dimensions thereof, particularly for applications on mobile devices such as personal computers, mobile phones and the like.
This volume reduction has been obviously allowed also by the technology evolution and by the increase in the functions which can be integrated in a single chip wherein the power device is realized.
Moreover, the need to reduce the package dimension and weight increases with the higher and higher miniaturization of the power devices comprised therein.
In particular, the package size and the weight have considerably reduced over the last few years and, through the most recent technologies, the ratio between the highest “chip size” and the “package footprint” went from about 0.3 in the early nineties to about 0.8 at the end of the century.
The continous progresses in the microprocessor technology have also led to an increase in the operating frequency of power devices thus increasing the field of application thereof.
Obviously, in order to keep the power at the high operating frequencies, the current supplied to the devices, and thus the power density distributed on the printed circuit board wherein they are assembled, must be increased. Consequently, the printed circuit board parasitic components contribute to generate losses both in the static and in the dynamic performances of the installed devices.
Moreover, the operating frequency increase also calls for a particular attention in reducing the parasitic inductances both in the package and on the printed circuit board. It is thus important that packages have such a configuration as to ease the assembly in parallel of more units on the board.
In the particular case of a package for a power device better performances can be obtained by reducing the device output resistance as well as the parasitic capacitances and the protective body or envelope thermal resistance.
In fact, as it is well known, a Q-factor (FFOM) to evaluate the power package efficiency is the product of the output resistance (Ron) and of the package occupation area (foot print).l The lower is this value, the more efficient is the package.
European patent application no. 0179714 by Thomson-CFS describes a first known solution to realize a power device package, schematically shown in FIG. 1. This solution provides the replacement of bonding wires (which traditionally allow the electronic device contact pad to be electrically connected with corresponding connection pins of the package incorporating them) with bridge copper foils. Therefore the resistive contributions linked to the device-package connections and to the current distribution on the device surface, as well as the thermal resistance thereof, are reducted, as it can be seen in the table of FIG. 4.
Although advantageous under several aspects, this first known technical solution has however a notable package size, thus keeping the package Q-factor high.
A second known solution, variously developed, is represented by a power device realized by means of a metal container, conveniently shaped, which brings the device drain on the same level as the upper surface thereof. An example of this embodiment is shown in FIG. 2 and described in the document MOSFET BGA design guide—Fairchild Semiconductor—August 2002. This solution allows the device output resistance to be reduced, since wire connections are missing, and the package occupation area to be reduced, since a protection resin is missing. Moreover, the metal container allows the heat exchange with the outside to be increased.
Although advantageous under several aspects, this second known technical solution has some drawbacks linked to the coplanarity between the metal container and the flat surface. Moreover, the resin absence makes the device more subject to the external environment effects with subsequent problems in terms of reliability in time.
It is also known to realize so-called vertical conduction multi-die packages. This embodiment provides that dies or power devices are arranged the one onto the other. This solution allows the assembled silicon area to be doubled, but at the detriment of the package thickness. An example of this technique is shown in FIG. 3 and described in U.S. patent application No. 2002/0096748 wherein two back-welded devices are used, through a back to back arrangement, in correspondence with the metal frame sides.
This known solution, although advantageous under some aspects, requires a connection between the power device source and gate terminals which traditionally occurs by means of wires, thus increasing the output resistance. Moreover, in the assembly step, this embodiment requires a device locking system suitable to prevent the same from moving from the positions thereof during a welding compound thermal reflow process (US 2002/0096748) and a double passage in the bonding equipments in order to connect the other electrodes of the two devices.
The technical problem underlying the present invention is to realize a vertical conduction power electronic device package having such structural and functional features as to allow drawbacks mentioned with reference to the prior art to be overcome and as to be consistent with the traditional surface assembly methods in order not to increase the production and assembly cost on the printed circuit board.